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description intended for analog and digital satellite receivers, this single low noise block converter regulator (lnbr) is a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to an lnb down converter via coaxial cable. the a8293 requires few external components, with the boost switch and compensation circuitry integrated inside of the device. a high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. the high levels of component integration ensure extremely low noise and ripple figures. the a8293 has been designed for high efficiency, utilizing the allegro ? advanced bcd process. the integrated boost switch has been optimized to minimize both switching and static losses. to further enhance efficiency, the voltage drop across the tracking regulator has been minimized. for diseqc? communications, several schemes are available for generating tone signals, all the way down to no-load, and using either the internal clock or an external time source. 8293-ds, rev. 4 features and benefits ? 2-wire serial i 2 c? -compatible interface: control (write) and status (read) ? lnb voltages (8 programmable levels) compatible with all common standards including domestic japan models ? tracking switch-mode power converter for lowest dissipation ? integrated converter switches and current sensing ? provides up to 700 ma load current ? static current limit circuit allows full current at startup and 13 18 v output transition; reliably starts wide load range ? push-pull output stage minimizes 13 18 v and 18 13 v output transition times for highly capacitive loads ? adjustable rise/fall time via external timing capacitor ? built-in tone oscillator, factory-trimmed to 22 khz facilitates diseqc? tone encoding, even at no-load ? four methods of 22 khz tone generation, via i 2 c? data bits and/or external pin ? auxiliary modulation input ? lnb overcurrent with timer ? diagnostics for output voltage level, input supply uvlo single lnb supply and control voltage regulator continued on the next page? functional block diagram a8293 lx boost converter lnb boost vin tcap 10 nf (or 22 nf) clock divider vcp v out d3 and d4 are used for surge protection. 100 nf sda scl add fault monitor ocp png tsd vuv extm v dd v s irq charge pump oscillator regulator vreg tcap f sw f sw 22 khz extm tgate tmode gndlx dac lnb voltage control wave shape linear stage c4 10 nf c9 220 nf c10 c7 100 nf c8 c3 220 nf r1 r2 r3 l1 33 h d1 d2 r4 d4 d3 a a a gnd i 2 c?- compatible interface 100 f c2 100 f c 5 1 f c6 pad nf c1 100 packages: 20-contact, 4 4 mm mlp/qfn (suffix es) 28 contact, 5 5 mm mlp/qfn (suffix et) for recommended external components, refer to table 7
single lnb supply and control voltage regulator a8293 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package thermal characteristics* package r ja (c/w) pcb es 37 (estimated) 4-layer et 32 4-layer * additional information is available on the allegro website. selection guide part number packing 1 description A8293SESTR-T 2 7 in. reel, 1500 pieces/reel 12 mm carrier tape es package, mlp/qfn surface mount 4 mm 4 mm 0.75 mm nominal height a8293settr-t 2,3 7 in. reel, 1500 pieces/reel 12 mm carrier tape et package, mlp/qfn surface mount 5 mm 5 mm 0.90 mm nominal height 1 contact allegro for additional packing options. 2 leadframe plating 100% matte tin. 3 this variant is in production but has been determined to be not for new design. this classi cation indicates that sale of this device is currently restricted to existing customer applications. the variant should not be purchased for new design ap - plications because obsolescence in the near future is probable. status date change september 21, 2010. a comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good. the device uses a 2-wire bidirectional serial interface, compatible with the i 2 c? standard, that operates up to 400 khz. the a8293 is supplied in two lead (pb) free mlp/qfn packages: es, 20-contact, 4 mm 4 mm, 0.75 nominal overall height, and et, 28-contact, 5 mm 5 mm, 0.90 nominal overall height. description (continued) absolute maximum ratings characteristic symbol conditions rating units load supply voltage, vin pin v in 30 v output current 1 i out internally limited a output voltage, boost pin ?0.3 to 33 v output voltage, lnb pin surge 2 ?1 to 33 v output voltage, lx pin ?0.3 to 30 v output voltage, vcp pin v cp ?0.3 to 41 v logic input voltage, extm pin ?0.3 to 5 v logic input voltage, other pins ?0.3 to 7 v logic output voltage ?0.3 to 7 v operating ambient temperature t a ?20 to 85 c junction temperature t j (max) 150 c storage temperature t stg ?55 to 150 c 1 output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the speci- fied current ratings, or a junction temperature, t j , of 150c. 2 use allegro recommended application circuit.
single lnb supply and control voltage regulator a8293 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pad 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 lnb gnd lx vin nc nc gnd vreg sda add float gnd nc scl irq boost vcp tcap float extm terminal list table name number function es et add 10 11 address select float 4, 15 5, 22 these pins must not be connected to anything; do not ground these pins boost 1 1 tracking supply voltage to linear regulator extm 5 6 external modulation input gnd 7, 14 8, 19 signal ground gndlx 19 27 boost switch ground irq 11 14 interrupt request lnb 20 28 output voltage to lnb lx 18 26 inductor drive point nc 6, 13, 16 4, 7, 13, 15- 18, 20, 21, 23, 24 no connection pad pad pad exposed pad; connect to the ground plane, for thermal dissipation scl 12 12 i 2 c?-compatible clock input sda 9 10 i 2 c?-compatible data input/output tcap 3 3 capacitor for setting the rise and fall time of the lnb output vcp 2 2 gate supply voltage vin 17 25 supply input voltage vreg 8 9 analog supply device pin-out diagram (top view) pad 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 lnb gndlx lx vin nc nc float gnd vreg sda add scl nc irq nc nc gnd nc nc nc nc boost vcp tcap nc float extm nc es package et package
single lnb supply and control voltage regulator a8293 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = 25c, v in = 9 to 16 v, unless noted otherwise 1 characteristics symbol test conditions min. typ. max. units general set-point accuracy, load and line regulation err relative to selected v lnb target level, i load = 0 to 450 ma ?3.0 ? +3.0 % supply current i in(off) enb bit = 0, lnb output disabled, v in = 12 v ? ? 10.0 ma i in(on) enb bit = 1, lnb output enabled, i load = 0 ma, v in = 12 v ? ? 19.0 ma boost switch on resistance r ds(on)boost i load = 450 ma ? 300 ? m switching frequency f sw 320 352 384 khz switch current limit i limsw v in = 9 v, v out = 19.0 v ? 2.7 ? a linear regulator voltage drop ? v reg v boost ? v lnb , no tone signal, i load = 450 ma ? 800 ? mv tcap pin current i chg tcap capacitor (c7) charging ?12.5 ?10 ?7.5 a i dischg tcap capacitor (c7) discharging 7.5 10 12.5 a output voltage rise time 2 t r(vlnb) for v lnb 13 18 v; c tcap = 5.6 nf, i load = 450 ma ? 500 ? s output voltage pull-down time 2 t f(vlnb) for v lnb 18 13 v; c load = 100 f, i load = 0 ma ? 12.5 ? ms output reverse current i rlnb enb bit = 0, v lnb = 33 v , boost capacitor (c5) fully charged ?15ma ripple and noise on lnb output 3 v rip,n(pp) 20 mhz bwl; reference circuit shown in functional block diagram; contact allegro for additional information on application circuit board design ?30?mv pp protection circuitry output overcurrent limit 4 i limlnb v boost ? v lnb = 800 mv ? 700 800 ma overcurrent disable time t dis ?48?ms vin undervoltage lockout threshold v uvlo v in falling 7.05 7.35 7.65 v vin turn on threshold v in(th) v in rising 7.40 7.70 8.00 v undervoltage hysteresis v uvlohys ? 350 ? mv thermal shutdown threshold 2 t j ? 165 ? c thermal shutdown hysteresis 2 ? t j ?20?c power not good flag set png set with respect to v lnb 77 85 93 % power not good flag reset png reset with respect to v lnb 82 90 98 % power not good hysteresis png hys with respect to v lnb ?5?% tone tone frequency f tone 20 22 24 khz tone amplitude, peak-to-peak v tone(pp) i load = 0 to 450 ma, c load = 750 nf 400 620 800 mv continued on the next page?
single lnb supply and control voltage regulator a8293 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com tone duty cycle dc tone i load = 0 to 450 ma, c load = 750 nf 40 50 60 % tone rise time t rtone i load = 0 to 450 ma, c load = 750 nf 5 10 15 s tone fall time t ftone i load = 0 to 450 ma, c load = 750 nf 5 10 15 s extm logic input v extm(h) 2.0 ? ? v v extm(l) ? ? 0.8 v extm input leakage i extmlkg ?1 ? 1 a i 2 c?-compatible interface logic input (sda,scl) low level v scl(l) ? ? 0.8 v logic input (sda,scl) high level v scl(h) 2.0 ? ? v logic input hysteresis v i2cihys ? 150 ? mv logic input current i i2ci v i2ci = 0 to 7 v ?10 <1.0 10 a logic output voltage sda and irq v t2cout(l) i load = 3 ma ? ? 0.4 v logic output leakage sda and irq v t2clkg v t2cout = 0 to 7 v ? ? 10 a scl clock frequency f clk ? ? 400 khz output fall time t fi2cout v t2cout(h) to v t2cout(l) ? ? 250 ns bus free time between stop/start t buf 1.3 ? ? s hold time start condition t hd:sta 0.6 ? ? s setup time for start condition t su:sta 0.6 ? ? s scl low time t low 1.3 ? ? s scl high time t high 0.6 ? ? s data setup time t su:dat 100 ? ? ns data hold time t hd:dat for t hd:dat (min) , the master device must provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the scl signal falling edge 0 ? 900 ns setup time for stop condition t su:sto 0.6 ? ? s i 2 c? address setting add voltage for address 0001,000 address1 0 ? 0.7 v add voltage for address 0001,001 address2 1.3 ? 1.7 v add voltage for address 0001,010 address3 2.3 ? 2.7 v add voltage for address 0001,011 address4 3.3 ? 5.0 v 1 operation at 16 v may be limited by power loss in the linear regulator. 2 guaranteed by worst case process simulations and system characterization. not production tested. 3 lnb output ripple and noise are dependent on component selection and pcb layout. refer to the application schematic and pcb la yout recommendations. not production tested. 4 current from the lnb output may be limited by the choice of boost components. electrical characteristics (continued) at t a = 25c, v in = 9 to 16 v, unless noted otherwise 1 characteristics symbol test conditions min. typ. max. units i 2 c? interface timing diagram t su:sta t hd:sta t su:dat t hd:dat t buf t su:sto t high t low sda scl
single lnb supply and control voltage regulator a8293 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com protection the a8293 has a wide range of protection features and fault diag- nostics which are detailed in the status register section. boost converter/linear regulator the a8293 solution contains a tracking current-mode boost converter and linear regulator. the boost converter tracks the requested lnb voltage to within 800 mv, to minimize power dissipation. under conditions where the input voltage, v boost , is greater than the output voltage, v lnb , the linear regulator must drop the differential voltage. when operating in these conditions, care must be taken to ensure that the safe operating temperature range of the a8293 is not exceeded. the boost converter operates at 352 khz typical: 16 times the internal 22 khz tone frequency. all the loop compensation, current sensing, and slope compensation functions are provided internally. the a8293 has internal pulse-by-pulse current limiting on the boost converter and dc current limiting on the lnb output to protect the ic against short circuits. when the lnb output is shorted, the lnb output current is limited to 700 ma typical, and the ic will be shut down if the overcurrent condition lasts for more than 48 ms. if this occurs, the a8293 must be reenabled for normal operation. the system should provide sufficient time between successive restarts to limit internal power dissipation; a minimum of 2 s is recommended. at extremely light loads, the boost converter operates in a pulse-skipping mode. pulse skipping occurs when the boost voltage rises to approximately 450 mv above the boost target output voltage. pulse skipping stops when the boost voltage drops 200 mv below the pulse skipping level. in the case that two or more set top box lnb outputs are con- nected together by the customer (e.g., with a splitter), it is pos- sible that one output could be programmed at a higher voltage than the other. this would cause a voltage on one output that is higher than its programmed voltage (e.g., 19 v on the output of a 13 v programmed voltage). the output with the highest voltage will effectively turn off the other outputs. as soon as this voltage is reduced below the value of the other outputs, the a8293 output will auto-recover to their programmed levels. charge pump. generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. slew rate control. during either start-up, or when the output voltage at the lnb pin is transitioning, the output voltage rise and fall times can be set by the value of the capacitor connected from the tcap pin to gnd (c tcap or c7 in the applications schematic). note that during start-up, the boost pin is pre- charged to the input voltage minus a voltage drop. as a result, the slew rate control for the boost pin occurs from this voltage. the value of c tcap can be calculated using the following for- mula: c tcap = ( i tcap 6) / sr , where sr is the required slew rate of the lnb output voltage, in v/s, and i tcap is the tcap pin current specified in the data sheet. the recommended value for c tcap , 10 nf, should provide satisfactory operation for most applications. however, in some cases, it may be necessary to increase the value of c tcap to avoid activating the current limit of the lnb output. one such situa- tion is when two set-top boxes are connected in parallel. if this is the case, the following formula can be used to calculate c tcap : c tcap (i tcap 6)(2 c boost ) / i limlnb , c tcap (10 a 6)(2 100 f) / 500 ma = 24 nf . the minimum value of c tcap is 2.2 nf. there is no theoretical maximum value of c tcap however too large a value will prob- ably cause the voltage transition specification to be exceeded. tone generation is unaffected by the value of c tcap . pull-down rate control. in applications that have to operate at very light loads and that require large load capacitances (in the order of tens to hundreds of microfarads), the output linear stage provides approximately 40 ma of pull-down capability. this ensures that the output volts are ramped from 18 v to 13 v in a reasonable amount of time. odt (overcurrent disable time) if the lnb output current exceeds 700 ma, typical, for more than 48 ms, then the lnb output will be disabled and the ocp bit will be set. short circuit handling if the lnb output is shorted to ground, the lnb output current will be clamped to 700 ma, typical. if the short circuit condition lasts for more than 48 ms, the a8293 will be disabled and the ocp bit will be set. auto-restart after a short circuit condition occurs, the host controller should periodically reenable the a8293 to check if the short circuit has functional description
single lnb supply and control voltage regulator a8293 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com been removed. consecutive startup attempts should allow at least 2 s of delay between restarts. in-rush current at start-up or during an lnb reconfiguration event, a tran- sient surge current above the normal dc operating level can be provided by the a8293. this current increase can be as high as 700 ma, typical, for as long as required, up to a maximum of 48 ms. tone generation the a8293 solution offers four options for tone generation, providing maximum flexibility to cover every application. the extm pin (external modulation), in conjunction with the i 2 c? control bits: tmode (tone modulation) and tgate (tone gate), provide the necessary control. the tmode bit controls whether the tone source is either internal or external (via the extm pin). both the extm pin and tgate bit determine the 22 khz con- trol, whether gated or clocked. four options for tone generation are shown in figure 1. note that when using option 4, when extm stops clocking, the lnb volts park at the lnb voltage, either plus or minus half the tone signal amplitude, depending on the state of extm. for example, if the extm is held low, the lnb dc voltage is the lnb pro- grammed voltage minus 325 mv (typical). extm tmode tgate tone (lnb ref) lnb (v) extm tmode tgate tone (lnb ref) lnb (v) extm tmode tgate tone (lnb ref) lnb (v) extm tmode tgate tone (lnb ref) lnb (v) option 1 ? use internal tone, gated by the tgate bit. option 2 ? use internal tone, gated by the extm pin. option 3 ? use external tone, gated by the tgate bit. option 4 ? use external tone. figure 1. options for tone generation
single lnb supply and control voltage regulator a8293 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i 2 c?-compatible interface this is a serial interface that uses two bus lines, scl and sda, to access the internal control and status registers of the a8293. data is exchanged between a microcontroller (master) and the a8293 (slave). the clock input to scl is generated by the master, while sda functions as either an input or an open drain output, depending on the direction of the data. timing considerations the control sequence of the communication through the i 2 c?- compatible interface is composed of several steps in sequence: 1. start condition. defined by a negative edge on the sda line, while scl is high. 2. address cycle. 7 bits of address, plus 1 bit to indicate read (1) or write (0), and an acknowledge bit. the first five bits of the address are fixed as: 00010. the four optional addresses, de- fined by the remaining two bits, are selected by the add input. the address is transmitted msb first. 3. data cycles. write ? 6 bits of data and 2 bits for addressing four internal control registers, followed by an acknowledge bit. see control register section for more information. read ? two status registers, where register 1 is read first, followed by register 2, then register 1, and so on. at the start of any read sequence, register 1 is always read first. data is transmitted msb first. 4. stop condition. defined by a positive edge on the sda line, while scl is high. except to indicate a start or stop condi- tion, sda must be stable while the clock is high. sda can only be changed while scl is low. it is possible for the start or stop condition to occur at any time during a data transfer. the a8293 always responds by resetting the data transfer sequence. the read/write bit is used to determine the data transfer direc- tion. if the read/write bit is high, the master reads the contents of 1 2 3 4 5 6 7 8 9 0 0 0 1 0 a1 a0 0 ak ak i0 d5 d4 d3 d2 d1 d0 i1 control data address start w stop sda scl 0 0 0 1 0 a1 a0 1 ak d6 d5 d4 d3 d2 d1 d0 d7 nak status register 1 address start r stop 1 2 3 4 5 6 7 8 9 sda scl 0 0 0 1 0 a1 a0 1 ak d6 d5 d4 d3 d2 d1 d0 d7 - - - d3 d2 d1 d0 - ak nak status data in register 2 address start r stop status data in register 1 1 2 3 4 5 6 7 8 9 sda scl acknowledge from lnbr acknowledge from lnbr acknowledge from lnbr no acknowledge from master no acknowledge from master acknowledge from lnbr acknowledge from lnbr write to register read one byte from register read multiple bytes from register figure 2. i 2 c? interface. read and write sequences.
single lnb supply and control voltage regulator a8293 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com register 1, followed by register 2 if a further read is performed. if the read/write bit is low, the master writes data to one of the two control registers. note that multiple writes are not permitted. all write operations must be preceded with the address. the acknowledge bit has two functions. it is used by the mas- ter to determine if the slave device is responding to its address and data, and it is used by the slave when the master is reading data back from the slave. when the a8293 decodes the 7-bit ad- dress field as a valid address, it responds by pulling sda low during the ninth clock cycle. during a data write from the master, the a8293 also pulls sda low during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received. in both cas- es, the master device must release the sda line before the ninth clock cycle, in order to allow this handshaking to occur. during a data read, the a8293 acknowledges the address in the same way as in the data write sequence, and then retains control of the sda line and send the data from register 1 to the master. on completion of the eight data bits, the a8293 releases the sda line before the ninth clock cycle, in order to allow the master to acknowledge the data. if the master holds the sda line low dur- ing this acknowledge bit, the a8293 responds by sending the data from register 2 to the master. data bytes continue to be sent to the master until the master releases the sda line during the acknowledge bit. when this is detected, the a8293 stops sending data and waits for a stop signal. interrupt request the a8293 also provides an interrupt request pin, irq, which is an open-drain, active-low output. this output may be connect- ed to a common irq line with a suitable external pull-up and can be used with other i 2 c?-compatible devices to request attention from the master controller. the irq output becomes active when either the a8293 first recognizes a fault condition, or at power-on, when the main sup- ply, v in , and the internal logic supply, v reg , reach the correct operating conditions. it is only reset to inactive when the i 2 c? master addresses the a8293 with the read/write bit set (caus- ing a read). fault conditions are indicated by the tsd, vuv, and ocp bits, and are latched in the status register. see the status register section for full description. the dis and png status bits do not cause an interrupt. the png bit is continually updated, apart from the dis bit, which changes when the lnb is either disabled, faulted, or is enabled. when the master recognizes an interrupt, it addresses all slaves connected to the interrupt line in sequence, and then reads the status register to determine which device is requesting atten- tion. the a8293 latches all conditions in the status register until the completion of the data read. the action at the resampling point is further defined in the status register section. the bits in the status register are defined such that the all-zero condition in- dicates that the a8293 is fully active with no fault conditions. when v in is initially applied, the i 2 c?-compatible interface does not respond to any requests until the internal logic supply v reg has reached its operating level. once v reg has reached this point, the irq output goes active, and the vuv bit is set. after the a8293 acknowledges the address, the irq flag is reset. after the master reads the status registers, the registers are updated with the vuv reset. 0 0 0 1 0 a1 a0 1 ak d6 d5 d4 d3 d2 d1 d0 d7 nak status register 1 address start r stop 1 2 3 4 5 6 7 8 9 sda scl irq fault event reload status register read after interrupt figure 3. i 2 c? interface. read sequences after interrupt request.
single lnb supply and control voltage regulator a8293 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com control registers (i 2 c?-compatible write register) all main functions of the a8293 are controlled through the i 2 c?- compatible interface via the 8-bit control registers. as the a8293 contains numerous control options, it is necessary to have two control registers. each register contains up to 6 bits of data (bit 0 to bit 5), followed by 2 bits for the register address (bit 6 and bit 7). the power-up states for the control functions are all 0s. the following tables define the control bits for each address and the settings for output voltage: table 1. control register address (i1, i0) = 00 bit name function 0 vsel0 see table 3, output voltage amplitude selection 1 vsel1 2 vsel2 3 vsel3 0: lnb = low range 1: lnb = high range 4 odt 1 (recommended): the odt functions are always enabled, but setting 1 recommended at all times. 5 enb 0: disable lnb output 1: enable lnb output 6 i0 address bit: 0 7 i1 address bit: 0 bit 0 vsel0 these three bits provide incremental control over the voltage on the lnb output. bit 1 vsel1 the available voltages provide the necessary levels for all the common standards bit 2 vsel2 plus the ability to add line compensation in increments of 333 mv. the voltage levels are defined in table 3, output voltage amplitude selection. bit 3 vsel3 switches between the low level and high level output voltages on the lnb output. 0 selects the low level voltage and 1 selects the high level. the low-level center voltage is 12.709 v nominal and the high level is 18.042 v nominal. these may be increased in steps of 333 mv using the vsel2, vsel1 and vsel0 control register bits. bit 4 odt the overcurrent disable timer is always enabled. bit 5 enb enables the lnb output. when set to 1 the lnb output is switched on. when set to 0, the lnb output is disabled. bit 6 i0 address bit 7 i1 address
single lnb supply and control voltage regulator a8293 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 2. control register address (i1, i0) = 10 bit name function 0 tmode 0: external tone 1: internal tone 1 tgate 0: tone gated off 1: tone gated on 2 - not used (0 recommended) 3 - not used 4 - not used 5 - not used 6 i0 address bit: 0 7 i1 address bit: 1 bit 0 tmode tone mode. selects between the use of an external 22 khz logic signal or the use of the internal 22 khz oscillator to control the tone generation on the lnb output. a 0 selects the external tone and a 1 selects the internal tone. see the tone generation section for more information bit 1 tgate tone gate. allows either the internal or external 22 khz tone signals to be gated, unless the extm is selected for gating. when set to 0, the selected tone (via tmode) is off. when set to 1, the selected tone is on. see tone generation section for more information. bit 2 ? not used. bit 3 ? not used. bit 4 ? not used. bit 5 ? not used. bit 6 i0 address. bit 7 i1 address.
single lnb supply and control voltage regulator a8293 12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 3. output voltage amplitude selection vsel3 vsel2 vsel1 vsel0 lnb (v) 0000 12.709 0001 13.042 0010 13.375 0100 14.042 0111 15.042 1000 18.042 1010 18.709 1011 19.042
single lnb supply and control voltage regulator a8293 13 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com status registers (i 2 c?-compatible read register) the main fault conditions: overcurrent (ocp), undervoltage (vuv) and overtemperature (tsd), are all indicated by setting the relevant bits in the status registers. in all fault cases, once the bit is set, it remains latched until the a8293 is read by the i 2 c? master, assuming the fault has been resolved. the current status of the lnb output is indicated by the dis- able bit, dis. the dis bit is set when either a fault occurs or if the lnb is disabled intentionally. this bit is latched, and is reset when the lnb is commanded on again. the power not good (png) is the only bit which may be reset without an i 2 c? read sequence. t able 4 summarizes the condition of each bit when set and how it is reset. as the a8293 has a comprehensive set of status reporting bits, it is necessary to have two status registers. when performing a multiple read function, register 1 is read followed by register 2, then register 1 again and so on. whenever a new read function is performed, register 1 is always read first. the normal sequence of the master in a fault condition will be to detect the fault by reading the status registers, then rereading the status registers until the status bit is reset indicating the fault condition is reset. the fault may be detected either by continuously polling, by responding to an interrupt request (irq), or by detect- ing a fault condition externally and performing a diagnostic poll of all slave devices. note that the fully-operational condition of the status registers is all 0s, to simplify checking of the status bit. table 4. status register bit setting status bit function set reset condition ? not used ? not used dis lnb disabled, either intentionally or due to fault latched lnb enabled and no fault ocp overcurrent latched i 2 c? read and fault removed png power not good non-latched lnb volts in range ? not used ? not used tsd thermal shutdown latched i 2 c? read and fault removed vuv undervoltage latched i 2 c? read and fault removed
single lnb supply and control voltage regulator a8293 14 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 5. status register 1 bit name function 0 dis lnb output disabled 1 ? not used 2 ocp overcurrent 3 ? not used 4 png power not good 5 ? not used 6 tsd thermal shutdown 7 vuv v in undervoltage bit 0 dis lnb output disabled. dis is used to indicate the current condition of the lnb output. at power-on, or if a fault condition occurs, dis will be set. this bit changing to 1 does not cause the irq to activate because the lnb output may be disabled in- tentionally by the i 2 c? master. this bit will be reset at the end of a write sequence if the lnb output is enabled. bit 1 ? not used. bit 2 ocp overcurrent. if the lnb output detects an overcurrent condition, for greater than 48 ms, the lnb output will be disabled. the ocp bit will be set to indicate that an overcurrent has occurred and the disable bit, dis, will be set. the status register is updated on the rising edge of the 9 th clock pulse in the data read sequence, where the ocp bit is reset in all cases, allowing the master to reenable the lnb output. if the overcurrent timer is not enabled, the device operate in current limit indefinitely and the ocp bit will be set. if the overcurrent condition is removed, the ocp bit will automatically be reset. note that if the overcurrent operates long enough, and a ther- mal shutdown occurs, the lnb output will be disabled and the tsd bit will be set. bit 3 ? not used. bit 4 png power not good. set to 1 when the lnb output is enabled and the lnb voltage is below 85% of the programmed voltage. the png is reset when the lnb volts are within 90% of the programmed lnb voltage. bit 5 ? not used. bit 6 tsd thermal shutdown. 1 indicates that the a8293 has detected an overtemperature condition and has disabled the lnb output. the disable bit, dis, will also be set. the status of the overtemperature condition is sampled on the rising edge of the 9 th clock pulse in the data read sequence. if the condition is no longer present, then the tsd bit will be reset, allowing the master to reenable the lnb output if required. if the condition is still present, then the tsd bit will remain at 1. bit 7 vuv undervoltage lockout. 1 indicates that the a8293 has detected that the input sup- ply, v in is, or has been, below the minimum level and an undervoltage lockout has occurred disabling the lnb outputs. the disable bit, dis, will also be set and the a8293 will not reenable the output until so instructed by writing the relevant bit into the control registers. the status of the undervoltage condition is sampled on the rising edge of the 9 th clock pulse in the data read sequence. if the condition is no longer present, then the vuv bit will be reset allowing the master to reenable the lnb out- put if required. if the condition is still present, then the vuv bit will remain at 1.
single lnb supply and control voltage regulator a8293 15 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 6. status register 2 bit name function 0 ? not used 1 ? not used 2 ? not used 3 ? not used 4 ? not used 5 ? not used 6 ? not used 7 ? not used bit 0 ? not used. bit 1 ? not used. bit 2 ? not used. bits 3 to 7 not used.
single lnb supply and control voltage regulator a8293 16 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 7. component selection table component characteristics manufacturer device c1, c4, c8 100 nf, 50 v, x5r or x7r, 0603 c2, c5 100 f, 35 v min , esr < 75 m , i ripple > 700 ma panasonic: eeu-fm1h101b chemicon: ekze500ell101mhb5d nichicon: uhc1v101mpt c3 220 nf, 10 v min , x5r or x7r, 0402 or 0603 c6 1.0 f, 25 v min , x5r or x7r, 1206 tdk: c3216x7r1e105k murata: grm31mr71e105ka01 taiyo yuden: tmk316bj105kl-t kemet: c1206c105k3ractu c7 10 nf, 10 v min , x5r or x7r, 0402 or 0603 c9 10 nf, 50 v, x5r or x7r, 0402 or 0603 c10 220 nf, 50 v, x5r or x7r, 0805 d1, d2 schottky diode, 40 v, 1 a, sod-123 diodes, inc: b140hw-7 central semi: cmmsh1-40 d3 schottky diode, 40 v, 3 a, sma sanken: sfpb-74 vishay: b340a-e3/5at diodes, inc.: b340a-13-f central senmi: cmsh3-40ma d4 tvs, 20 v rm , 32 v cl at 500 a (8/20 s), 3000 w st:lnbtvs6-221s littelfuse: smdj20a l1 33 ? h, i sat > 2.6 a, dcr < 90 m tdk: tsl1112ra-330k2r3-pf taiyo yuden: lhlc10tb330k coilcraft: dr0810-333l r1 to r4 determined by v dd , bus capacitance, etc.
single lnb supply and control voltage regulator a8293 17 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package es 20-pin mlp/qfn 0.95 c seating plane c 0.08 21x 20 20 2 1 1 2 20 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only, not for tooling use (reference dwg-2864, jedec mo-220 wggd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn50p400x400x80-21bm) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.30 0.50 4.10 0.50 0.75 0.05 2.45 2.45 0.25 +0.05 ?0.07 0.40 0.10 4.00 0.10 4.00 0.10 2.45 2.45 b pcb layout reference view
single lnb supply and control voltage regulator a8293 18 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package et 28-pin mlp/qfn 0.25 +0.05 ?0.07 0.55 +0.20 ?0.10 0.50 0.90 0.10 c 0.08 29x seating plane c a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220vhhd-1) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 qfn50p500x500x100-29v1m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 28 2 1 a 28 1 2 pcb layout reference view b 3.15 3.15 3.15 3.15 0.30 1 28 0.50 1.15 4.80 4.80 c 5.00 0.15 5.00 0.15 d d coplanarity includes exposed thermal pad and terminals
single lnb supply and control voltage regulator a8293 19 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i 2 c? is a trademark of philips semiconductors. diseqc? is a trademark of eutelsat s.a. copyright ?2007-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 4 march 12, 2012 update output voltage amplitude

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